1. Field of the Invention
This invention relates to a method for soldering a multiple-lead semiconductor element (LSI) having multiple leads such as a large-capacity memory controller, a DRAM, etc. on a wiring board.
2. Description of Related Art
Recently, a high-density semiconductor circuit (a large-scale integration: LSI) circuit having multiple lead terminals has been developed in order to satisfy a requirement for making a semiconductor circuit high density. In addition, in order to miniaturize the LSI circuit as described above, a wiring board having thereon a wiring pattern which is so designed that a wiring pattern interval and a land interval of the wiring pattern are set to fine pitch (0.5 mm) has been frequently used.
FIG. 1(A) is a schematic diagram showing a conventional soldering method of soldering a QFP type of semiconductor circuit (LSI) on a fine-pitch wiring pattern. In FIG. 1(A), a reference numeral 1 represents a surface mount device (SMD) having multiple lead terminals 2 projected from the bottom surface thereof, and a reference numeral 3 represents a fine-pitch wiring pattern having plural land portions, which is formed on a print board.
Each of the lead terminals 2 of the SMD 1 is so designed to have the width below 0.2 mm and the thickness below 100 .mu.m, for example, and the dimensional precision of each lead terminal has an error of several %. Therefore, when an ordinary soldering method is conducted on such lead terminals 2 of the SMD 1, failure of soldering occurs due to lead float, defective soldering, etc. after the SMD 1 is actually mounted on the wiring board, so that yield of a semiconductor circuit is reduced and its reliability is lowered.
In order to overcome the above disadvantage, the following soldering method has been conventionally conducted on the SMD 1. That is, a soldering plating is beforehand conducted on the wiring pattern side, the SMD 1 is positioned on the wiring pattern 3 so that the lead terminals 2 are positionally coincident with the land portions of the wiring pattern 3, and then the lead terminals 2 are heated from their upper sides by a heat press thereby soldering the lead terminals 2 on the wiring pattern 3. However, in this method, it is difficult to perform the connection between the lead terminals 2 and the land portions 3 with sufficient amount of solder because the soldering plating enables solder to be laminated merely in 30 .mu.m thickness at maximum. In addition, the soldering plating contains a large amount of tin, and thus its connection strength is low.
In order to perform the soldering with large amount of solder by the heat press, flux-cored cream solder is coated on predetermined portions (land portions) of the wiring pattern by a screen printing method or the like, and then the multiple lead terminals are heated under press by the heat press, thereby soldering the SMD 1 on the wiring pattern. In this case, if sufficient amount of cream solder is fed, the cream solder 4 is coated on the land portions of the wiring pattern in semi-paste form as shown in FIG. 1(B). Thereafter, the lead terminals 2 of the SMD 1 is mounted on the cream solder 4, and then pushed against the cream solder 4 while heated by the heat press (trowel), so that the lead terminals 2 are soldered onto the wiring pattern 3 through the cream solder 4. Thereafter, the heat press is cooled, and then is drawn up, thereby completing the soldering process.
In the above method, if the amount of cream solder is sufficient, the soldering with sufficient strength can be conducted. However, the surface shape of the cream solder becomes hemispherical as shown in FIG. 1(B), so that when the lead terminals 2 are pushed by the heat press, each lead terminal is applied with a force in a direction as indicated by an arrow which is laterally deviated from the center portion of the lead terminal.
Since the dimensional precision of the lead terminals of the SMD 1 can not be set to a high value, there occurs a problem that when the SMD 1 is soldered on a wiring pattern of fine pitch, a soldering bridge frequently occurs due to irregularity of pitch interval of the wiring pattern.